1. Field of the Invention
The present invention relates to a ferroelectric storage device and a test method thereof. More particularly, the present invention relates to a ferroelectric storage device which includes a memory element (memory cell) including a switching transistor and a ferroelectric capacitor and which memorizes information depending on a polarization direction of the ferroelectric capacitor, and a test method thereof.
2. Description of the Related Art
FIG. 13 shows a hysteresis loop exhibiting a characteristic of a ferroelectric capacitor. The horizontal axis indicates a voltage V applied between both electrode ends of the ferroelectric capacitor. The vertical axis indicates the amount of polarization Pr. A ferroelectric memory utilizing the hysteresis characteristic of the ferroelectric capacitor is used as a non-volatile memory, and a variety of its applications are currently proposed.
FIG. 14 shows a structure of a memory cell of a ferroelectric storage device. A memory storage operation of the memory cell will be described with reference to FIG. 13.
When xe2x80x9cHxe2x80x9d data is written to the memory cell, a bit line is transitioned to the xe2x80x9cHxe2x80x9d level and a plate line is transitioned to the xe2x80x9cLxe2x80x9d level while a word line is transitioned to the xe2x80x9cHxe2x80x9d level so that a MOS transistor is in the ON state. The polarization state of a ferroelectric capacitor in this situation is indicated by A in FIG. 13. When the bit line is transitioned to the xe2x80x9cLxe2x80x9d level, the potential of the ferroelectric capacitor is zero volts, but the polarization remains (this state is indicated by B in FIG. 13).
When xe2x80x9cLxe2x80x9d data is written to the memory cell, the bit line is transitioned to the xe2x80x9cLxe2x80x9d level and the plate line is transitioned to the xe2x80x9cHxe2x80x9d level while the word line is transitioned to the xe2x80x9cHxe2x80x9d level so that the MOS transistor is in the ON state. The polarization state of a ferroelectric capacitor in this situation is indicated by D in FIG. 13. Thereafter, when the plate line is transitioned to the xe2x80x9cLxe2x80x9d level, the voltage applied to the ferroelectric capacitor is zero volts, but an inverted polarization remains (this state is indicated by E in FIG. 13).
To read out information, the bit line is transitioned to the xe2x80x9cLxe2x80x9d level and a pulse of xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d is applied to the plate line while the word line is transitioned to the xe2x80x9cHxe2x80x9d level so that the MOS transistor is in the ON state. In this case, the ferroelectric capacitor in which the xe2x80x9cHxe2x80x9d data is written is transitioned to B to C to D to E, so that the polarization is inverted. In contrast, the ferroelectric capacitor in which the xe2x80x9cLxe2x80x9d data is written is transitioned to E to D to E, so that the polarization is not changed.
Thus, in the ferroelectric capacitor, a destructive readout is executed which leads to a change in information in the memory cell due to the readout operation. The change of the polarization causes a change in the amount of electric charge output from the ferroelectric capacitor, which appears as a small difference in potential in the bit line. Such a small difference in potential is amplified by a sense amplifier (not shown) so as to be read out as data.
A ferroelectric capacitor is categorized into the following two types: a ferroelectric memory (hereinafter referred to as a xe2x80x9c1T1C-type ferroelectric memoryxe2x80x9d) in which one memory cell includes one transistor and one ferroelectric capacitor; and a ferroelectric memory (hereinafter referred to as a xe2x80x9c2T2C-type ferroelectric memoryxe2x80x9d) in which one memory cell includes two transistors and two ferroelectric capacitors.
FIG. 7 shows a circuit of a conventional 1T1C-type ferroelectric memory 700. The 1T1C-type ferroelectric memory 700 includes a memory cell MC which is shown in FIG. 14. The memory cell MC is connected to a word line WL, a plate line PL, a bit line BIT0, and a bit line BIT1. The 1T1C-type ferroelectric memory 700 includes a memory cell ref_MC for generating a reference potential which is used as a reference used in determining whether data written in the memory cell MC is the xe2x80x9cHxe2x80x9d data or the xe2x80x9cLxe2x80x9d data. The memory cell ref_MC is connected to a reference word line Ref_WL, a reference plate line Ref_PL, bit lines BIT0 and BIT1, and bit lines BIT0# and BIT1# paired with the respective bit lines BIT0 and BIT1. The reference memory cell ref_MC outputs data having an intermediate level between the xe2x80x9cHxe2x80x9d data and the xe2x80x9cLxe2x80x9d data output from the memory cell MC, by short-circuiting an output of the memory cell MC in which the xe2x80x9cHxe2x80x9d data is written and an output of the memory cell MC in which the xe2x80x9cLxe2x80x9d data is written.
FIG. 8 is a timing chart used for explaining an operation of the conventional 1T1C-type ferroelectric memory 700. Initially, using a Row control circuit and a Ref_Cell control circuit, the word line WL and the reference word line Ref_WL are transitioned to the xe2x80x9cHxe2x80x9d level, and then pulses (readout pulses) are applied to the plate line PL and the reference plate line Ref_PL. In this case, pulses having the same potential are applied to the respective plate line PL and plate line Ref_PL. When, using a Row control circuit and a Ref_Cell control circuit, the word line WL and the reference word line Ref_WL are transitioned to the xe2x80x9cHxe2x80x9d level, and then pulses (readout pulses) are applied to the plate line PL and the reference plate line Ref_PL, the xe2x80x9cHxe2x80x9d data or the xe2x80x9cLxe2x80x9d data is output from the memory cell MC to the bit lines BIT0 and BIT1. Similarly, data having a reference level is output from the reference memory cell Ref_MC to the bit lines BIT0# and BIT1#. Thereafter, an SAE (Sense Amp. Enable) is transitioned to the xe2x80x9cHxe2x80x9d level so that the sense amplifier (Sense Amp.) is actuated and the potential difference between both bit lines is amplified.
Such data is read out in reading out information (the operation is hereinafter also referred to as a xe2x80x9cREAD operationxe2x80x9d). To avoid a destructive readout of information from a storage device, a rewrite operation is performed in the memory cell MC using a rewrite pulse. In writing information (the operation is hereinafter referred to as a xe2x80x9cWRITE operationsxe2x80x9d), the difference in potential between both bit lines is amplified, and thereafter write data (data to be written) is transferred to a bit line before the rewrite pulse is applied to the memory cell MC. Thereafter, the data is written to the memory cell MC using the rewrite pulse. When a READ or WRITE operation to the memory cell MC is performed in the 1T1C-type ferroelectric memory 700, the xe2x80x9cLxe2x80x9d level of a pulse applied to a plate line is typically zero volts and the xe2x80x9cHxe2x80x9d level is typically VCC. During the time that the rewrite operation is executed using the rewrite pulse, the reference word line Ref_WL is transitioned to the xe2x80x9cLxe2x80x9d level so that the reference cell Ref_MC is cut off a bit line, and initial data for generating data having the reference level is written to the reference cell Ref_MC. For example, the reference memory cell ref_MC generates data having the reference level by generating data having an intermediate level between the xe2x80x9cHxe2x80x9d data and the xe2x80x9cLxe2x80x9d data output from the memory cell MC. The intermediate-level data is obtained by short-circuiting an output of the memory cell MC in which the xe2x80x9cHxe2x80x9d data is written and an output of the memory cell MC in which the xe2x80x9cLxe2x80x9d data is written. In this case, the xe2x80x9cHxe2x80x9d data and the xe2x80x9cLxe2x80x9d data are written to difference memory cells in order to cause the reference memory cell ref_MC to generate the reference-level data.
FIG. 9 shows another conventional 1T1C-type ferroelectric memory 900. The 1T1C-type ferroelectric memory 900 includes a Ref_Level generation circuit in order to generate a reference voltage instead of the reference memory cell ref_MC included in the 1T1C-type ferroelectric memory 700. The Ref_Level generation circuit divides a resistance between VCC and GND so that data having an intermediate level between the xe2x80x9cHxe2x80x9d data and the xe2x80x9cLxe2x80x9d data can be output.
FIG. 10 is a timing chart used for explaining another conventional 1T1C-type ferroelectric memory 900. Initially, the word line WL is transitioned to the xe2x80x9cHxe2x80x9d level by the Row control circuit, and a pulse (read pulse) is applied to the plate line PL. Thereby, the xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d data is output to the bit lines BIT0 and BIT1. Further, the RGE (Ref_Level generation circuit enable) is transitioned to the xe2x80x9cHxe2x80x9d level so that the Ref_Level generation circuit is enabled, and data having a reference level is output to the bit lines BIT0 and BIT1. Thereafter, the SAE is transitioned to the xe2x80x9cHxe2x80x9d level so that the sense amplifier (Sense Amp.) is actuated. The difference in potential between both bit lines is amplified by the sense amplifier.
Such data is read out in a READ operation. A rewrite operation is performed in the memory cell MC using a rewrite pulse. In a WRITE operation, the difference in potential between both bit lines is amplified, and thereafter write data is transferred to a bit line before the rewrite pulse is applied to the memory cell MC. Thereafter, the data is written to the memory cell MC using the rewrite pulse. When a READ or WRITE operation to the memory cell MC is performed in the 1T1C-type ferroelectric memory 900, the xe2x80x9cLxe2x80x9d level of a pulse applied to a plate line is typically zero volts and the xe2x80x9cHxe2x80x9d level is typically VCC.
FIG. 11 shows a conventional 2T2C-type ferroelectric memory 1100. The 2T2C-type ferroelectric memory 1100 includes a memory cell MC of FIG. 14. The memory cell MC is connected to a word line WL0 and a plate line PL0, or a word line WL1 and a plate line PL1. The 2T2C-type ferroelectric memory 1100 includes two memory cells MC. One of the two memory cells MC is connected to a bit line BIT0 or BIT1. The other is connected to a bit lines BIT0# or BIT1# paired with the respective bit line BIT0 or BIT1.
FIG. 12 is a timing chart used for explaining an operation of the 2T2C-type ferroelectric memory 1100. Initially, the word line WL0 (or WL1) is transitioned to the xe2x80x9cHxe2x80x9d level by the Row control circuit, and a pulse (read pulse) is applied to a plate line PL0 (or PL1). Thereby, the xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d data is output from one memory cell MC to bit line BIT0 or BIT1. The reverse data is output from the other memory cell MC to bit line BIT0# or BIT1#. Thereafter, the SAE is transitioned to the xe2x80x9cHxe2x80x9d level so that the sense amplifier (Sense Amp.) is actuated. The difference in potential between both bit lines is amplified by the sense amplifier.
Such data is read out in a READ operation. A rewrite operation is performed in the memory cell MC using a rewrite pulse. In a WRITE operation, the difference in potential between both bit lines is amplified, and thereafter write data is transferred to a bit line before the rewrite pulse is applied to the memory cell MC. Thereafter, the data is written to the memory cell MC using the rewrite pulse. When a READ or WRITE operation to the memory cell MC is performed in the 2T2C-type ferroelectric memory 1100, the xe2x80x9cLxe2x80x9d level of a pulse applied to a plate line is typically zero volts and the xe2x80x9cHxe2x80x9d level is typically VCC.
A characteristic of a ferroelectric capacitor is important for both 1T1C-type and 2T2C-type ferroelectric memories. There are variations in the characteristic of the ferroelectric capacitor due to a manufacturing process. Further, the characteristic of the ferroelectric capacitor is significantly unstable compared with other memories (DRAM, SRAM, etc.). Therefore, to ensure reliability and operation stability equal to those of other memories, a quality test more stringent than that for the other memories is required for a ferroelectric memory.
Therefore, for example, Japanese Laid-open Publication No. 11-149796 discloses the following method. An offset is provided in a sense amplifier so as to detect a memory cell in which only a potential less than or equal to the offset can be detected. Thereby, a ferroelectric storage device including a memory cell having a small readout margin can be detected in advance.
FIG. 15 shows a typical latch sense amplifier 1500. FIG. 16 shows a latch sense amplifier 1600 described in Japanese Laid-open Publication No. 11-149796. The latch sense amplifiers 1500 and 1600 each includes a pair of bit lines BIT and BIT#, a sense amplifier SAP, an n-type transistor n, and a p-type transistor p.
However, the latch sense amplifier 1600 consists of eight elements. Therefore, the area of the latch sense amplifier 1600 is larger than the typical latch sense amplifier 1500 consisting of four elements. One latch sense amplifier 1500 or 1600 is provided between each pair of bit lines. Therefore, there is a problem in that the area of the sense amplifier is considerably increased in order to produce a ferroelectric memory having ensured high reliability and operation stability by the method disclosed in Japanese Laid-open Publication No. 11-149796.
According to one aspect of the present invention, a ferroelectric storage device comprises a memory cell including a first ferroelectric capacitor and connected to a first bit line, wherein the memory cell memorizes data based on a polarization of the first ferroelectric capacitor, and the memory cell outputs a first amount of electric charge generated by a change in the polarization of the first ferroelectric capacitor to the first bit line in reading out the data, a reference cell including a second ferroelectric capacitor and connected to a second bit line, wherein the reference cell outputs as a reference level a second amount of electric charge generated by a change in the polarization of the second ferroelectric capacitor to the second bit line, an amplifier for comparing the first amount of electric charge with the second amount of electric charge to read out data, a first amount-of-electric-charge setting section for setting the first amount of electric charge to an arbitrary level, and a second amount-of-electric-charge setting section for setting the second amount of electric charge to an arbitrary level.
In one embodiment of the present invention, at least one of the first and second amount-of-electric-charge setting sections applies a voltage to at least one of the first and second ferroelectric capacitors so that at least one of the first and second amounts of electric charge is set to an arbitrary level.
In one embodiment of the present invention, the first and second amount-of-electric-charge setting sections consist of an input pad or an input pin capable of externally receiving an arbitrary potential.
In one embodiment of the present invention, when a pulse is applied to an electrode at one side of the first ferroelectric capacitor so that the data is read out or written, the first and second amount-of-electric-charge setting sections adjust a potential of at least one of an xe2x80x9cHxe2x80x9d level and an xe2x80x9cLxe2x80x9d level of the pulse.
In one embodiment of the present invention, the setting of the first and second amount-of-electric-charge setting sections is performed at least one of when the data is read out and-when the data is written.
According to another aspect of the present invention, a method is provided for testing the above-described ferroelectric storage device. In the method, a memory cell having a small margin is detected by changing the voltage applied to the ferroelectric storage device in such a manner as to reduce the first amount of electric charge.
According to another aspect of the present invention, a method is provided for testing the above-described ferroelectric storage device. In the method, a memory cell having a small margin is detected by changing a voltage applied to the ferroelectric storage device in such a manner as to reduce a difference between the first amount of electric charge and the second amount of electric charge.
According to another aspect of the present invention, a ferroelectric storage device comprises a memory cell including a first ferroelectric capacitor and connected to a first bit line, wherein the memory cell memorizes data based on a polarization of the first ferroelectric capacitor, and the memory cell outputs a first amount of electric charge generated by a change in the polarization of the first ferroelectric capacitor to the first bit line in reading out the data, a reference level generation circuit connected to a second bit line, for generating a second amount of electric charge as a reference level to be output to the second bit line, an amplifier for comparing the first amount of electric charge with the second amount of electric charge to read out data, and at least one amount-of-electric-charge setting section for setting at least one of the first amount of electric charge and the second amount of electric charge to an arbitrary level.
In one embodiment of this invention, the at least one amount-of-electric-charge setting section applies a voltage to at least one of the first and second ferroelectric capacitors so that at least one of the first and second amounts of electric charge is set to an arbitrary level.
In one embodiment of this invention, the at least one amount-of-electric-charge setting section consists of an input pad or an input pin capable of externally receiving an arbitrary potential.
In one embodiment of this invention, when a pulse is applied to an electrode at one side of the first ferroelectric capacitor so that the data is read out or written, the at least one amount-of-electric-charge setting section adjusts a potential of at least one of an xe2x80x9cHxe2x80x9d level and an xe2x80x9cLxe2x80x9d level of the pulse.
In one embodiment of this invention, the setting of the at least one amount-of-electric-charge setting section is performed at least one of when the data is read out and when the data is written.
According to another aspect of the present invention, a method is provided for testing the above-described ferroelectric storage device. In the method, a memory cell having a small margin is detected by changing a voltage applied to the ferroelectric storage device in such a manner as to reduce the first amount of electric charge.
According to another aspect of the present invention, a method is provided for testing the above-described ferroelectric storage device. In the method, a memory cell having a small margin is detected by changing a voltage applied to the ferroelectric storage device in such a manner as to reduce a difference between the first amount of electric charge and the second amount of electric charge.
According to another aspect of the present invention, a ferroelectric storage device comprises a memory cell including first and second ferroelectric capacitors and connected to first and second bit lines, wherein the memory cell memorizes data based on polarizations of the first and second ferroelectric capacitors, and in reading out the data, the memory cell outputs a first amount of electric charge generated by a change in the polarization of the first ferroelectric capacitor to the first bit line, and outputs a second amount of electric charge generated by a change in the polarization of the second ferroelectric capacitor to the second bit line, an amplifier for comparing the first amount of electric charge with the second amount of electric charge to read out data, and at least one amount-of-electric-charge setting section for setting at least one of the first amount of electric charge and the second amount of electric charge to an arbitrary level.
In one embodiment of this invention, the at least one amount-of-electric-charge setting section applies a voltage to at least one of the first and second ferroelectric capacitors so that at least one of the first and second amounts of electric charge is set to an arbitrary level.
In one embodiment of this invention, the at least one amount-of-electric-charge setting section consists of an input pad or an input pin capable of externally receiving an arbitrary potential.
In one embodiment of this invention, when a pulse is applied to an electrode at one side of each of the first and second ferroelectric capacitors so that the data is read out or written, the at least one amount-of-electric-charge setting section adjusts a potential of at least one of an xe2x80x9cHxe2x80x9d level and an xe2x80x9cLxe2x80x9d level of the pulse.
In one embodiment of this invention, the setting of the at least one amount-of-electric-charge setting section is performed at least one of when the data is read out and when the data is written.
According to another aspect of the present invention, a method is provided for testing the above-described ferroelectric storage device. In the method, a memory cell having a small margin is detected by changing a voltage applied to the ferroelectric storage device in such a manner as to reduce the first amount of electric charge.
According to another aspect of the present invention, a method is provided for testing the above-described ferroelectric storage device. In the method, a memory cell having a small margin is detected by changing a voltage applied to the ferroelectric storage device in such a manner as to reduce a difference between the first amount of electric charge and the second amount of electric charge.
Hereinafter, functions of the present invention will be described.
In Japanese Laid-open Publication No. 11-149796, an offset is provided in a sense amplifier so as to detect a memory cell in which only a potential less than or equal to the offset can be detected. The present invention provides a method for adjusting the amount of electric charge output from a ferroelectric capacitor to a bit line.
In a 1T1C-type ferroelectric memory, a readout margin for a memory cell can be intentionally reduced by: (1) making it possible to externally adjust an output level (reference level) of a reference cell or a reference level generation circuit using a test circuit (potential generation circuit), an input pin (test pin), an input pad (test pad), or the like; (2) making it possible to externally adjust the potential of a pulse applied to a plate line using a test circuit, an input pin, an input pad, or the like, where a reference level is fixed, so that the amount of electric charge read out from a memory cell in testing is reduced; or (3) adjusting a level applied to a bit line in writing.
In a 2T2C-type ferroelectric memory, a readout margin for a memory cell can be intentionally reduced by: (1) making it possible to externally adjust the potential of a pulse applied to a plate line using a test circuit, an input pin, an input pad, or the like, where a reference cell is not used, so that the amount of electric charge read out from a memory cell in testing is reduced and the difference in level between a pair of bit lines is reduced; or (2) adjusting a level applied to a bit line in writing.
According to the present invention, a ferroelectric storage device which can use the sense amplifer 1500 can be designed only by providing a simple peripheral circuit, i.e., a test circuit (potential generation circuit) or providing a test pin or a test pad through which an arbitrary voltage can be externally input. The area of the test circuit, the test pin, the test pad, or the like is much smaller than the area of a sense amplifier. Therefore, as is different from conventional technology, a ferroelectric storage device including a memory cell having a small margin can be rejected without expansion of the area of a sense amplifier.
Thus, the invention described herein makes possible the advantages of providing a small-size ferroelectric storage device and a test method thereof, in which a memory cell having a small readout margin can be detected.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.